Recent advances in MOS LSI (metal oxide semiconductor large scale integration) has pushed semiconductor technology to the 0.18 μm geometry and beyond. Transistor manufacturing methods are adopting patterning methods that use an inorganic antireflective film formed from such materials as silicon oxynitride (SiON) and a dual gate process that prevents depletion of the gate electrode.
When a gate electrode is patterned using an antireflective film, it becomes necessary to remove the antireflective film from the polycrystalline silicon (also referred to as poly-Si) gate electrode after etching the gate. A hot phosphoric acid solution is generally used for this removal. However, when a poly-Si gate that has been implanted with phosphorous in a dual gate process is etched, shape defects result.
The shape defects associated with the conventional art etch process are shown in FIG. 7, which is an SEM (scanning electron microscope) photomicrograph of a gate cross section of a FET (field effect transistor). The notching in the gate is clearly evident.
The conventional technology for manufacturing a semiconductor device having a gate is typified by Takegawa et al., Japanese Patent 2000100965, published Apr. 7, 2000. In Takegawa, as is shown in FIG. 1, a compensating film 51 is formed on a hard mask 41 used for etching a gate electrode 30. The structure of the semiconductor device also includes a SI substrate 10, an oxide layer 20, a poly-Si layer 31 and a WSi2 layer 32. The compensating film 51 is formed of poly-Si, which is the same as the poly-Si used to form the gate electrode 30. As shown in FIG. 2, the compensating film 51 is completely removed while the etching is carried out. The hard mask 41 is not exposed to the etching gas and is therefore prevented from being thinned while etching is performed. The mask 41 prevents ions from penetrating it during ion injection. However, Takegawa fails to offer any technology to prevent the formation of notches in the gate.
In the conventional gate formation technologies, the defects that can occur depend on the type of etching process. Wet etching with phosphoric acid (H3PO4) can result in the formation of a notch in the gate, and the notch will result in high resistivity and degradation of the transistor. Although notch formation can be prevented, to an extent, by the application of a layer of photoresist, the photoresist has a limited effectiveness in preventing notch formation. The application of photoresist also entails additional process steps and reagent cost that result in a less economically viable transistor manufacturing process.
On the other hand, a dry etching process tends to form recesses in the silicon. These recesses will result in a degradation of the transistor. As a result, both wet and dry etching to form a gate structure pose numerous difficulties in the conventional art.
As has been discussed above, the conventional gate manufacturing technology tends to form unacceptable notching in the gate during the etching process. Accordingly, new technologies are required for the 0.18 μm geometry and beyond.